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ENGINEERING, TE 2025 HSC 3 MC

The truth table represents the basic operation of a logic gate.

\begin{array}{|c|c|c|}
\hline
\rule{0pt}{2.5ex}\ \ \ \textit{Input A} \ \ \ \rule[-1ex]{0pt}{0pt}&\ \ \ \textit{Input B} \ \ \ & \ \ \ \textit{Output} \ \ \ \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt}& 1 & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt}& 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt}& 1 & 1 \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt}& 0 & 0 \\
\hline
\end{array}

What is the logic gate?

  1. AND
  2. NAND
  3. NOR
  4. OR
Show Answers Only

\(D\)

Show Worked Solution
  • An OR gate produces an output of 1 whenever at least one input is 1, and an output of 0 only when both inputs are 0.
  • The truth table shows Output = 1 for all input combinations except (0, 0), which is the defining behaviour of an OR gate.
  • An AND gate requires both inputs to be 1 to produce an output of 1 — eliminated by rows where one input is 0 yet the output is 1.
  • NAND and NOR gates are inverted versions of AND and OR respectively — their outputs would be reversed from those shown.

\(\Rightarrow D\)

ENGINEERING, TE 2024 HSC 26b

To avoid overloading a cellular network, a logic gate is used to control the activation of a signal booster.

The signal booster will only activate when both of the following conditions are met:

  • the signal strength falls below an acceptable level
  • the network traffic flow falls below an acceptable level.

Complete a truth table for this scenario and identify a suitable logic gate.   (3 marks)

Truth table:

\begin{array} {|c|c|c|}
\hline
\rule{0pt}{2.5ex} \quad \textit{Acceptable signal} \quad & \quad \textit{Acceptable traffic} \quad & \quad \textit{Activate booster} \quad \\
\textit{strength} \rule[-2ex]{0pt}{0pt} & \textit{flow} & \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} & &  \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} & &  \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} & &  \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} & &  \\
\hline
\end{array}

Logic gate: ....................

Show Answers Only

Truth table:

\begin{array} {|c|c|c|}
\hline
\rule{0pt}{2.5ex} \quad \textit{Acceptable signal} \quad & \quad \textit{Acceptable traffic} \quad & \quad \textit{Activate booster} \quad \\
\textit{strength} \rule[-2ex]{0pt}{0pt} & \textit{flow} & \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} 1 & 1 & 0 \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} 1 & 0 & 0 \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} 0 & 1 & 0 \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} 0 & 0 & 1 \\
\hline
\end{array}
Logic gate: NOR
Show Worked Solution

Truth table:

\begin{array} {|c|c|c|}
\hline
\rule{0pt}{2.5ex} \quad \textit{Acceptable signal} \quad & \quad \textit{Acceptable traffic} \quad & \quad \textit{Activate booster} \quad \\
\textit{strength} \rule[-2ex]{0pt}{0pt} & \textit{flow} & \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} 1 & 1 & 0 \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} 1 & 0 & 0 \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} 0 & 1 & 0 \\
\hline
\rule{0pt}{2.5ex} \rule[-2ex]{0pt}{0pt} 0 & 0 & 1 \\
\hline
\end{array}
Logic gate: NOR

ENGINEERING, TE 2023 HSC 24d

One of several fail-safe systems incorporated into a roller coaster design uses the following safety protocol.

Before a roller coaster car brake can be released to allow the roller coaster to commence its ride, ALL of the following conditions must be met:

    • passenger safety harnesses must be secured into place
    • the sensors must indicate the track is clear of obstructions
    • the ride entry and exit gates are locked.

   A logic gate schematic is shown.

  1. What is the purpose of the NAND gate in this schematic?   (2 marks)

  2. Complete the truth table for the logic gate schematic.   (3 marks)

\begin{array} {|c|c|c|c|}
\hline
\rule{0pt}{2.5ex} \textit{Safety harnesses} \rule[-1ex]{0pt}{0pt} & \textit{Track} & \textit{Ride gates are} & \textit{Operator} \\ \textit{secure} & \textit{is clear} & \textit{locked} & \textit{warning light} \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} & 0 & 0 &  \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} &  &  & 1 \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} & 1 & 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} &  &  &  \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} & 0 & 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} &  &  & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} &  &  & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} & 1 & 1 &  \\
\hline
\end{array}

Show Answers Only

i.    NAND gate purpose:

  • Ensures that if any or all of the inputs are zero the output will result in a 1 and thus turn on the warning light.
  • In effect, the warning light will remain ON until all conditions for safe operation are met.

ii.    

\begin{array} {|c|c|c|c|}
\hline
\rule{0pt}{2.5ex} \textit{Safety harnesses} \rule[-1ex]{0pt}{0pt} & \textit{Track} & \textit{Ride gates are} & \textit{Operator} \\ \textit{secure} & \textit{is clear} & \textit{locked} & \textit{warning light} \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} & 0 & 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} & 0 & 1 & 1 \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} & 1 & 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} & 1 & 1 & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} & 0 & 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} & 0 & 1 & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} & 1 & 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} & 1 & 1 & 0 \\
\hline
\end{array}

Show Worked Solution

i.     NAND gate purpose:

  • Ensures that if any or all of the inputs are zero the output will result in a 1 and thus turn on the warning light.
  • In effect, the warning light will remain ON until all conditions for safe operation are met.

ii.    

\begin{array} {|c|c|c|c|}
\hline
\rule{0pt}{2.5ex} \textit{Safety harnesses} \rule[-1ex]{0pt}{0pt} & \textit{Track} & \textit{Ride gates are} & \textit{Operator} \\ \textit{secure} & \textit{is clear} & \textit{locked} & \textit{warning light} \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} & 0 & 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} & 0 & 1 & 1 \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} & 1 & 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 0 \rule[-1ex]{0pt}{0pt} & 1 & 1 & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} & 0 & 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} & 0 & 1 & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} & 1 & 0 & 1 \\
\hline
\rule{0pt}{2.5ex} 1 \rule[-1ex]{0pt}{0pt} & 1 & 1 & 0 \\
\hline
\end{array}

ENGINEERING, TE 2018 HSC 15 MC

Which of the following electronic circuits functions as a NAND logic gate?
 

 

Show Answers Only

`D`

Show Worked Solution
  • NAND gates produce a high output (in this case turn the light on) as long as the 2 conditions are not BOTH met.
  • The gates in these diagrams represent inputs being met (closed) or not met (open).
  • In `D`, if both gates close the circuit will be complete without turning the light on as ‘both conditions have been met’. 

`=>D`


♦♦ Mean mark 34%.

ENGINEERING, TE 2018 HSC 21d

Digital logic controls a self-driving vehicle's brakes.
 

Brakes will be applied when all of the following conditions are met:

    • the motor is on
    • the vehicle is in motion
    • either sensor 1 or sensor 2 is activated.

Explain how the logic gates, labelled 1, 2 and 3 in the circuit below, control the vehicle's brakes.   (3 marks)
 

Show Answers Only
  1. Logic gate 1 – AND – both inputs must be ON for ON output
  2. Logic gate 2 – OR – either input ON to produce ON output
  3. Logic gate 3 – AND – both inputs must be ON for ON output (ie brakes are applied)
Show Worked Solution
  1. Logic gate 1 – AND – both inputs must be ON for ON output
  2. Logic gate 2 – OR – either input ON to produce ON output
  3. Logic gate 3 – AND – both inputs must be ON for ON output (ie brakes are applied)

ENGINEERING, TE 2017 HSC 23a

A digital TV receiver circuit uses logic gates as shown.
 

Complete the truth table for this logic circuit.   (2 marks)
 

Show Answers Only

\begin{array} {|c|c|c|}
\hline \ \text{A}\ & \text{B}\ & \text{Z}\ \\
\hline \ \ \ \ 0\ \ \ \  & \ \ \ \ 0 \ \ \ \ & \ \ \ \ 1\ \ \ \ \  \\
\hline \ 0 & 1 & 0 \\
\hline \ 1 & 0 & 0 \\
\hline \ 1 & 1 & 0 \\
\hline \end{array}

Show Worked Solution

\begin{array} {|c|c|c|}
\hline \ \text{A}\ & \text{B}\ & \text{Z}\ \\
\hline \ \ \ \ 0\ \ \ \  & \ \ \ \ 0 \ \ \ \ & \ \ \ \ 1\ \ \ \ \  \\
\hline \ 0 & 1 & 0 \\
\hline \ 1 & 0 & 0 \\
\hline \ 1 & 1 & 0 \\
\hline \end{array}

ENGINEERING, TE 2022 HSC 22b

In the event of a fall or a medical emergency, smart watches are designed to alert emergency services when either of the following conditions is met.

Condition 1: the smart watch emergency alert is manually activated

Condition 2: the smart watch detects a sudden fall and no movement for 1 minute

An incomplete logic diagram showing the activation of the smart watch is given.
 

Complete the diagram by identifying the inputs and drawing the appropriate logic gates.   (3 marks)

Show Answers Only

Show Worked Solution


Mean mark 54%.

ENGINEERING, TE 2020 HSC 21b

The diagram shows a simple logic circuit with inputs `A, B, C` and `D`, and output `Z`.
 

Inputs `A` and `D` are set to 'high' (1).

Determine, using the logic circuit diagram, the combination of inputs at `B` and `C` which will produce a high (1) output at `Z`. Use the truth table to support your answer.   (3 marks)
 

Show Answers Only

Let the output of the AND gate be `E` and the output of the OR gate be `F`

\begin{array} {|c|c|c|c|c|c|c|}
\hline  \   A  \  & \  B \  & \  C \  & \  D \  & \  E \  & \  F \  & \  Z   \\
\hline 1 & 1 & 0 & 1 & 1 & 1 & 0\\
\hline 1 & 1 & 1 & 1 & 1 & 1 & 0\\
\hline 1 & 0 & 1 & 1 & 0 & 1 & 0\\
\hline 1 & 0 & 0 & 1 & 0 & 1 & 0\\
\hline \end{array}

  • As shown in the table, since `D` is always on, the output of the OR gate (`F`) will always be on/1.
  • Therefore, `Z` will always be 0 since it is a NOR gate, i.e. it requires `E` and `F` to be 0, and `F` is always 1.
  • Hence, there are no inputs at `B` and `C` that produce a high output at `Z`.
Show Worked Solution

Let the output of the AND gate be `E` and the output of the OR gate be `F`

\begin{array} {|c|c|c|c|c|c|c|}
\hline  \   A  \  & \  B \  & \  C \  & \  D \  & \  E \  & \  F \  & \  Z   \\
\hline 1 & 1 & 0 & 1 & 1 & 1 & 0\\
\hline 1 & 1 & 1 & 1 & 1 & 1 & 0\\
\hline 1 & 0 & 1 & 1 & 0 & 1 & 0\\
\hline 1 & 0 & 0 & 1 & 0 & 1 & 0\\
\hline \end{array}

  • As shown in the table, since `D` is always on, the output of the OR gate (`F`) will always be on/1.
  • Therefore, `Z` will always be 0 since it is a NOR gate, i.e. it requires `E` and `F` to be 0, and `F` is always 1.
  • Hence, there are no inputs at `B` and `C` that produce a high output at `Z`.

ENGINEERING, TE 2021 HSC 16 MC

The circuit diagram shown includes two transistors in its configuration.
 

What type of logic gate has the same function as this pair of transistors in the circuit?

  1. OR gate
  2. NOR gate
  3. AND gate
  4. NAND gate
Show Answers Only

`A`

Show Worked Solution
  • If current/signal passes through A, B or both A & B, then the circuit is complete.
  • This is the same requirements as an OR logic gate.

`=>A`

♦ Mean mark 41%.